Performance analysis of blocking banyan switches

D.C. Vasiliadis, G.E. Rizos, and C. Vassilakis
Proceedings of the IEEE sponsored International Joint Conference on Computer, Information and System Sciences and Engineering - CIS²E 06.

Abstract:
Banyan Networks are a major class of Multistage Interconnection Networks (MINs). They have been widely used as efficient interconnection structures for parallel computer systems, as well as switching nodes for high-speed communication networks. The performance of them is mainly determined by their communication throughput and their mean packet delay. In this paper we use a model that is based on a universal performance factor, which includes the importance aspect of each of the above main performance factors (throughput and delay) in the design process of a MIN. The model can also uniformly be applied to several representative networks. The complexity of the model requires to be investigated by time-consuming simulations. In this paper we study a typical (8X8) Baseline Banyan Switch that consists of (2X2) Switching Elements (SEs). The objective of this simulation is to determine the optimal buffer size for the MIN stages under different conditions.

Note: This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder.