@conference {Vasiliadis200823,
	title = {Improving performance of finite-buffered blocking delta networks with 2-class priority routing through asymmetric-sized buffer queues},
	booktitle = {Proceedings - 4th Advanced International Conference on Telecommunications, AICT 2008},
	year = {2008},
	note = {cited By (since 1996) 1},
	month = {6},
	pages = {23-29},
	abstract = {In this paper the performance of asymmetric-sized finite-buffered Delta Networks with 2-class routing traffic is presented and analyzed in the uniform traffic conditions under various loads using simulations. We compare the performance of 2-class priority mechanism against the single priority one, by gathering metrics for the two most important network performance factors, namely packet throughput and delay. We also introduce and calculate a universal performance factor, which includes the importance aspect of each of the above main performance factors. We found that the use of asymmetric-sized buffered systems leads to better exploitation of network capacity, while the increments in delays can be tolerated. The goal of this paper is to help network designers in performance prediction before actual network implementation and in understanding the impact of each parameter factor. Β{\textcopyright} 2008 IEEE.},
	keywords = {Computer networks, Delta networks, International conferences, Performance factors},
	doi = {10.1109/AICT.2008.13},
	url = {http://www.scopus.com/inward/record.url?eid=2-s2.0-50949090335\&partnerID=40\&md5=1a38fdae7e54da27ace165ed90b5a386},
	author = {D.C. Vasiliadis and G.E. Rizos and Costas Vassilakis}
}
@conference {Vasiliadis2007,
	title = {Performance Analysis of dual priority single-buffered blocking Multistage Interconnection Networks},
	booktitle = {3rd International Conference on Networking and Services, ICNS 2007},
	year = {2007},
	month = {6},
	publisher = {IEEE},
	organization = {IEEE},
	abstract = {In this paper a novel architecture of dual priority single-buffered blocking Multistage Interconnection Networks (MINs) is presented. We analyzed their performance in the uniform traffic condition under various loads using simulations. We compared the dual priority architecture against a single priority MIN, by gathering metrics for the two most important network performance factors, namely packet throughput and the mean time a packet needs to traverse the network. We demonstrated the gain of the high priority packets against the low priority packets under different configuration schemas. In this paper we focus on studying the influence of the priority bit in the header field of transmitted packets on the performance of high and low priority traffic of a MIN. Performance prediction before actual network implementation and understanding the impact of parameter settings in a MIN setup are valuable assets for network designers for minimizing overall deployment costs and delivering efficient networks. Β{\textcopyright} 2007 IEEE.},
	keywords = {Computer architecture, Interconnection networks, International conferences, Low priority (LP), Metrics (CO), Multistage interconnection networks Multistage interconnection netowrk (MIN), Network architecture, Network designers, Network performances, Novel architecture, Packet throughput, Parameter estimation, Parameter settings, Performance analyses, Performance predictions, Schemas, Systems engineering, telecommunication, Telecommunication networks, Uniform traffic},
	doi = {10.1109/ICNS.2007.92},
	url = {http://www.scopus.com/inward/record.url?eid=2-s2.0-47049115567\&partnerID=40\&md5=148ac10a4b9facdaf1066911f87f5bb5},
	author = {D.C. Vasiliadis and G.E. Rizos and Costas Vassilakis}
}
